| Paper ID | ASPS-1.3 |
| Paper Title |
FPGA HARDWARE DESIGN FOR PLENOPTIC 3D IMAGE PROCESSING ALGORITHM TARGETING A MOBILE APPLICATION |
| Authors |
Faraz Bhatti, Thomas Greiner, Pforzheim University, Germany |
| Session | ASPS-1: Architectures |
| Location | Gather.Town |
| Session Time: | Tuesday, 08 June, 16:30 - 17:15 |
| Presentation Time: | Tuesday, 08 June, 16:30 - 17:15 |
| Presentation |
Poster
|
| Topic |
Applied Signal Processing Systems: Signal Processing Hardware [DIS-PROG, DIS-MLTC, DIS-SOCP] |
| IEEE Xplore Open Preview |
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| Virtual Presentation |
Click here to watch in the Virtual Conference |
| Abstract |
Over the past years, widespread use of applications based on 3D image processing has increased rapidly. It is being employed in various fields, such as research, medicine and automation. Plenoptic camera system is used to capture light-field that can be exploited to estimate the 3D depth of the scene. The respective algorithms consist of a large number of computation intensive instructions. It eventually leads to the problem of large execution time of the algorithm. Moreover, they require substantial amount of memory cells for the storage of intermediate and final results. Desktop GPU based solutions are power intensive and therefore cannot be used in the mobile applications with low energy requirements. The idea presented in this paper is to use the FPGA based hardware design to improve the performance of a 3D depth estimation algorithm by utilizing the advantage of concurrent execution. The algorithm is implemented, evaluated and the results show that FPGA design reduces the respective execution time significantly. |
